AMD Zen 2 microarchitecture will provide a 29% increase in the number of instructions per clock compared to the first generation Zen

AMD continues to share information on its upcoming Zen 2 microprocessor microarchitecture. improvement of such an indicator as the number of instructions per clock (IPC).

It is noted that the increase in this indicator for processors based on Zen 2 compared to chips based on the original Zen microarchitecture is an impressive 29%. This is almost 2 times higher than the initial expectations of about 16%, voiced earlier.

It is noted that AMD has conducted internal tests DKERN + RSA for calculations with integers and floating-point numbers. As a result, a performance index of 4.53 was obtained for processors based on the Zen 2 microarchitecture, while for devices based on the first generation Zen microarchitecture, this figure was 3.5. Thus, the increase in the number of instructions per clock is 29.4%. We add that the increase in this indicator is equivalent to the increase in single-core performance of the chip. . But Zen 2 already has a number of key differences compared to Zen +, which explains such a significant increase in IPC. When developing a new-generation microarchitecture, AMD engineers paid special attention to critical components: the kernel interface, the floating point computing unit.

Excavator. But in the case of Zen 2, a completely new kernel interface is used, which is better optimized for collecting and distributing workloads between various kernel components. At the same time, the block of operations with a floating point received a 256-bit capacity. Also, the Zen 2 microarchitecture has other improvements, for example, wider conveyors and windows, which together provide such a significant increase in the number of instructions per clock. These chips, known under the code name Rome, will receive up to 64 computing cores.

Source: techpowerup

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